An oscillation adjusting circuit may effectively be applied to a data transmission system, e.g. a Universal Serial Bus (USB) interface, a micro control unit (MCU), or a communication system, with bit-rate or clock synchronization and utilizes exact data clock synchronization control to ensure the correctness and the stability during the data packet transmission. Taking the full speed specification of the USB version 1.1 as an example on condition that the external crystal oscillator is not used, a mechanism of an internal circuit loop of the oscillation adjusting circuit is utilized to automatically detect and calibrate the oscillation frequency of the receiver device, so that the internal clock of the receiver can be synchronized with the reference data stream of the host.
The advantages utilizing the oscillation adjusting circuit are as follows. (1) The system may still be made to stably transmit data on condition that a highly exact external device (e.g. crystal oscillator) is not used. (2) The number of the pins of the integrated circuit may be saved, and the occupation space, on the layout surface of the system board, of the external device (e.g. crystal oscillator) may also be saved, so that the cost may be effectively reduced.
In the aspect of the circuit design, a conventional oscillation adjusting circuit adopts the architecture of the phase-locked loop (PLL) and/or the phase-delayed loop (DLL). Taking the data transmission specification of the USB as an example, the disadvantages of the architecture are as follows. (1) The conventional PLL or DLL requires a longer and sequential input reference clock to reach the lock. (2) It requires a lengthy locking time. (3) It requires an exact frequency-lock circuit configuration, or the error of the clock is easily formed. Based on the above reasons, the PLL or DLL is not very suitable for the transmission system of the USB.
The U.S. Pat. No. 6,670,852 discloses the prior art illustrating an oscillation adjusting circuit including a first circuit and a second circuit. The first circuit is configured to generate an output signal oscillating at a first frequency in response to a first control signal. The second circuit is configured to receive a calibration signal oscillating at a second frequency and generate the first control signal in response to a counter value when in a first mode and a stored value when in a second mode, wherein, while in the first mode, the counter value is adjusted in response to a difference between the first frequency and the second frequency.
The U.S. Pat. No. 7,093,151 discloses the prior art illustrating an oscillation adjusting circuit including a first circuit. The first circuit is configured to receive an input data stream, generate an output having a first frequency and adjust the first frequency in response to a measured duration of a known time interval associated with a period between a first occurrence of a predefined bit pattern and a second occurrence of the predefined bit pattern in the input data stream. This prior art requires a large lock-up table to memorize, adjust, and calibrate the internal frequency of the first circuit.
In order that the oscillation adjusting circuit does not use the external crystal and the lock-up table for reducing the chip area, saving the component cost, and providing good selectivity on the wide frequency domain of the communication transmission, a more effective oscillation adjusting circuit is required.